Abstract

Edge detection is a critical image processing operation and is a core aspect of feature extraction as well as object identification. In this paper, we introduce an uncomplicated pipelined hardware architecture for Sobel edge detection and Canny edge detection on an FPGA for comparing their edge detection performance, on-chip power, and resource usage. The Sobel edge method delivers computation simplicity and efficiency, while the Canny algorithm offers more robust and reliable detection of thin edges, which are important in enabling supporting technologies such as self-driving cars, computer vision, medical imaging, etc. It is thus important to have a dedicated hardware design for performing both edge detection algorithms on an embedded system, thereby reducing the dependency on the general processing part of the system. The hardware was designed using hardware description language (Verilog) and was implemented on the Zedboard FPGA. The Zedboard, containing all programmable SoC (AP SoC) Xilinx Zynq-7000, was used for the purpose of testing and analysis of input grayscale images. The edge detection accuracy, power utilization, and resource utilization of both algorithms are analysed in real-time. As a result, this work demonstrates that the Canny edge detection algorithm outperforms Sobel edge detection algorithm for its precise detection of thin edges when implemented on an FPGA. The latter algorithm uses less power and resources on the FPGA, but it can’t be used for critical applications.

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